Test insert containing vias for interfacing a device containing contact bumps with a test substrate

ABSTRACT

An insert is provided for testing a chip-scale-packaged microelectronic device having an encapsulant-protrusion and a ball-grid-array of outwardly-projecting contacts. The insert comprises a substrate of mono-crystalline silicon. Walls of the substrate define a plurality of pockets that are configured to receive and contact the outwardly-projecting contacts of the microelectronic device. Additional walls of the substrate define a recess disposed amongst the plurality of pockets. The recess has a width greater than the widths of any of the pockets. Additionally, the recess comprises a perimeter greater than that of the encapsulant-protrusion of the chip-scale-packaged microelectronic device, and a depth operative to clear the encapsulant-protrusion when the chip-scale package is seated upon the insert.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a test insert and method fortesting a microelectronic device. More particularly, the presentinvention provides a silicon insert for testing a chip-scale-packagedelectronic device having an encapsulant-protrusion and plurality ofoutwardly-projecting-contacts of a ball-grid-array.

[0002] A well known package of the microelectronics industry forsemiconductor die comprises a molded epoxy package having a plurality ofconductive pins that electrically interface the semiconductor die. Morerecently, however, the industry has developed smaller packages andinterface solutions that use solder balls arranged in an array disposedon a surface of an electronic device. The array of solder balls, knownas a ball-grid-array or bump-grid-array (BGA), permit smaller distancesbetween adjacent input/output lines and provide for greater input/outputdensity and lower costs for these devices.

[0003] One exemplary, prior art, package is the flip-chip, whichcomprises, with reference to FIG. 1, a plurality of outwardly-projectingelectrical contacts 14 placed directly upon a face 18 of a semiconductordie 12. The flip-chip 9 does not require bond wires between bond pads ofthe die and a lead frame of the more conventional pin-type packages (notshown). The solder balls or outwardly-projecting-contacts 14 of theflip-chip are preferably of the same size, for example, in the range of0.3 to 0.4 millimeters in diameter, and placed in an array having adistance between adjacent balls of, for example, about 1.5 mm. Theadvent of such BGA flip-chips led to the development of BGA testsockets.

[0004] Further referencing FIGS. 1-2, an exemplary prior art, BGA testsocket 10 comprises a substrate 1 1 having a plurality of pockets 16arranged in an array corresponding to the outwardly-projecting-contacts14 of a flip-chip 9. A layer of conductive material 20 is formed andpatterned over the substrate so as to provide conductive liners inpockets 16 and conductive traces over the substrate in electricalcommunication with the pockets. Such prior art, BGA test socket 10 isable to temporarily seat a flip-chip, microelectronic device andelectrically engage the outwardly-projecting contacts of its BGAinterface. During testing of the flip-chip packaged microelectronicdevice, the test socket and the flip-chip are biased together withpockets 16 of the test socket engaged with theoutwardly-projecting-contacts 14 of the flip-chip.

[0005] Recent trends of the semiconductor industry have led todevelopment of smaller size semiconductor die. At the same time, thenumber of input/output lines required for the die have remained the sameor have increased, thereby increasing their input/output densities. Toaccommodate these input/output density enhancements, the semiconductormanufactures have developed alternative chip-scale packages.

[0006] One such alternative chip-scale-package is known as a “globbed”chip-scale-package. With reference to FIGS. 3A, 3B, 3C, “globbed”chip-scale-package 38 comprises a semiconductor die 12 mounted to aninsulating support 32, also known as an interposer, which has an areaabout 1-2 times larger than die 12. Conductive lines 35 of interposer 32electrically couple and re-route the small-size, fine-pitch, interposerpads 34 associated with die 12 to larger size, standard pitch, BGAcontacts 14. The outwardly projecting contacts 14 of the interposer aredesigned in accordance, and for compliance, with conventional BGAstandards.

[0007] Further referencing FIG. 3A, encapsulant protrusion 36 of globbedchip-scale-package 38, is disposed between and amongst a plurality ofthe outwardly protruding contacts 14 of the chip-scale-package.Encapsulant protrusion 36 comprises a material, e.g., non-conductiveepoxy, suitable for enclosing interposer opening 31. Encapsulantprotrusion 36 protects and encases bond-wires 30 which bond-wiresbond-out and electrically couple terminals 29 of die 12 to conductivepads 34 of interposer 32. Encapsulant protrusion 36 of globbedchip-scale-package 38, with reference to FIG. 3C, usually has a heighth₂ beyond the face of interposer 32 less than the height h₁ of theoutwardly projecting contacts 14.

[0008] Prior art, BGA test inserts, for example the insert as shown inFIG. 1, may not provide reliable testing of the globbedchip-scale-packaged, microelectronic devices. When using such prior art,test insert to test globbed chip-scale-packaged, microelectronicdevices, a region of upper surface 19 of the test insert may contact theencapsulant protrusion 36 of the globbed chip-scale-packagedmicroelectronic device, so as to interfer and prevent engagement of itsoutwardly projecting-contacts 14 with respective pockets 16 of the testinsert 10.

[0009] What is needed is a BGA test socket for a globbedchip-scale-packaged, microelectronic device, which socket overcomes someof the problems of the prior art. What is also needed is a test insertcapable of providing full and reliable, temporary electrical engagementwith such microelectronic device. What is also needed is a method ofreliably testing a globbed chip-scale-packaged, microelectronic device.

SUMMARY OF THE INVENTION

[0010] The present invention relates to the formation of an insert forengaging a microelectronic device having outwardly projecting contactbumps. The insert may be known by such terms as a receptacle, a BGAsocket, an interconnect, a BGA test receiver, or silicon insert. Thepresent invention recognizes and overcomes problems of the prior artcaused by an encapsulant projection of a globbed chip-scale-packagedmicroelectronic device interfering with the interconnection of theinsert with the outwardly projecting contacts of the chip-scale-packagedmicroelectronic device.

[0011] In accordance with one embodiment of the present invention, aninsert is formed for seating and testing a chip-scale-packagedmicroelectronic device having a plurality of outwardly projectingcontacts and a protrusion. The substrate is formed with walls thatdefine a plurality of pockets configured to seat and engage theoutwardly projecting contacts of the chip-scale-package. Other walls ofthe substrate define a recess configured to receive with clearance theencapsulant protrusion of the chip-scale-package when the outwardlyprojecting contacts are seated in the plurality of pockets.

[0012] In accordance with one aspect of this exemplary embodiment, therecess has a perimeter encompassing an area greater that that of aplurality of the pockets.

[0013] In accordance with another aspect of the exemplary embodiment,the recess of the insert is formed simultaneously with the pockets andof equal depth.

[0014] In accordance with another exemplary embodiment of the presentinvention, an insert comprises a substrate having walls that define aplurality of pockets that are configured to receive the outwardlyprojecting contacts of a microelectronic device. Other walls of thesubstrate may define vias that pass through the substrate and are incommunication with associated pockets of the plurality. Conductivematerial fills the vias and lines a pocket connected to the via.

[0015] These and other features of the present invention will becomemore fully apparent in the following description and independent claims,or maybe learned by the practice of the invention as set forthhereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be understood from reading thefollowing description of the particular embodiments with reference tospecific embodiments illustrated in the intended drawings. Understandingthat these drawings depict only particular embodiments of the inventionand are not therefore to be considered limiting of its scope, theinvention will be described and explained with addition detail throughuse of the accompanying drawings in which:

[0017]FIG. 1 is a cross-sectional view of a known insert engaging aknown BGA flip-chip component;

[0018]FIG. 2 is a planar elevational view of a known insert wire-bondedto an underlying support substrate, showing an array of pockets of theinsert;

[0019]FIG. 3A is a cross-sectional view showing a known globbedchip-scale-packaged microelectronic device;

[0020]FIG. 3B is a cross-sectional view showing another globbedchip-scale-packaged microelectronic device of the prior art;

[0021]FIG. 3C is a partial cross-sectional view showing relative heightsof an ecncapsulate protrusion and outwardly projecting contacts of aknown, globbed chip-scale-packaged microelectronic device;

[0022]FIG. 4 is a cross-sectional view showing a globbedchip-scale-packaged microelectronic device seated upon an insert inaccordance with an exemplary embodiment of the present invention;

[0023]FIG. 5 is a cross-sectional view showing a substrate anddielectric layer during formation of an insert in accordance with anembodiment of the present invention;

[0024]FIG. 6 is a cross-sectional view of the structure of FIG. 5 afterfurther processing, showing patterned photoresist;

[0025]FIG. 7 is a cross-sectional view of the substrate and dielectriclayer of FIG. 6 after further processing, showing a mask over thesubstrate;

[0026]FIG. 8 is a partial planar elevational view of the substrate ofFIG. 7, showing an opening in a mask that exposes a region of theunderlying substrate;

[0027]FIG. 9 is a cross-sectional view of the substrate of FIG. 7 afterfurther processing, showing pockets and a recess;

[0028]FIG. 10 is a prospective view of the substrate of FIG. 9 afterfurther processing has removed a mask;

[0029]FIG. 11 is a cross-sectional view of the semiconductor structureafter further processing, showing conformal insulating and metal layerspatterned over portions of the substrate including the pockets, andadditionally showing the insert assembled within a test jig;

[0030]FIG. 12 is a partial planar elevation view showing a pocket of aninsert;

[0031]FIG. 13 is a partial cross-sectional view illustrating a pocket ofan insert engaging various size solder balls;

[0032]FIG. 14 is a cross-sectional view of a test jig showing amicroelectronic device seated upon and pressed against a test insert inaccordance with an embodiment of the present invention;

[0033]FIG. 15 is a partial cross-sectional view showing a pocket, viaand micro-bump structure of a test insert over a support substrate inaccordance with another embodiment of the present invention;

[0034]FIG. 16 is a partial cross-sectional view showing a substrate tobe processed in accordance with a further embodiment of the presentinvention;

[0035]FIG. 17 is a schematic cross-sectional view of the structure ofFIG. 16 after further processing, showing a mask over a substrate;

[0036]FIG. 18 is a representative cross-sectional view of the substrateof FIG. 17 after further processing, showing a pocket;

[0037]FIG. 19 is a cross-sectional view of the substrate of FIG. 18after further processing, showing a via through the substrate and incommunication with a pocket;

[0038]FIG. 20 is a cross-sectional view of the substrate of FIG. 19after further processing, showing a conformal layer of insulatingmaterial over the substrate including the walls of the via and pockets;

[0039]FIG. 21 is a cross-sectional view of the substrate of FIG. 20after further processing, showing two layers of conductive material overthe substrate;

[0040]FIG. 22 is a cross-sectional view of the substrate of FIG. 21after further processing, showing mask material over regions of thesubstrate associated with a pocket;

[0041]FIG. 23 is a cross-sectional view of the substrate of FIG. 22after further processing, showing patterned conductive layers;

[0042]FIG. 24 is a cross-sectional view of the substrate of FIG. 23after further processing, showing the via filled with conductivematerial and the pocket lined with the conductive material;

[0043] FIGS. 25-28 are schematic cross-sectional views illustrating amethod of forming a solder bump over a via filled with conductivematerial in accordance with an exemplary embodiment of the presentinvention; and

[0044]FIG. 29 is a cross-sectional view of a test jig for testing amicroelectronic device seated upon and pressed against a test insert.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] Reference will now be made to drawings wherein like structuresare provided like reference designations. The drawings arerepresentative, non-limiting diagrams of select embodiments of thepresent invention and are not necessarily drawn to scale.

[0046] The present invention relates to formation of an insert forreceiving and testing a “globbed” chip-scale-packaged microelectronicdevice having an array of outwardly projecting contacts, e.g., of aball-grid-array or bump-grid-array (BGA). Such insert may also be knownby other terms such as, for exemple, interconnect, interposer, socket,BGA test socket, or silicon insert.

[0047]FIG. 1 shows a cross-sectional view of a known flip-chip 9 seatedupon a known insert 10. Solder balls or outwardly projecting contacts 14of flip-chip 9 engage pockets 16 of insert 10. Inwardly facing surface18 of flip-chip 12 is kept in spaced relationship over surface 19 ofinsert 10. Patterned conductive material 20 of the insert electricallycouple pockets 16 to their associated pads 21 around the periphery ofthe insert 10. Typically, dielectric 22 insulates conductive material 20from substrate 11. Bonds wire 28 electrically couple the peripheral pads21 of insert 10 to conductive pads 24 of support substrate 26.

[0048] A planar elevational view, with reference to FIG. 2, showspockets 16 of insert 10 arranged in an array, which would correspond tothe BGA structure of a flip-chip (shown in phantom lines). Providingadditional detail, conductive traces 25 of patterned conductive material20 of insert 10, electrically couple pockets 16 to the pads 21 aroundthe periphery of insert 10, while bond wires 28 bound-out pads 21 of theinsert to the conductive pads 24 of support substrate 26.

[0049] Recent trends of the semiconductor industry have reducedsemiconductor die size, while increasing the number of input/outputinterconnects. These changes have lead to development of newerball-grid-array or bump-grid-array (i.e., BGA) interface solutionscpable of accommodating the smaller die of increased I/O densities. Onesuch exemplary, prior art, BGA interface package comprises the globbedchip-scale-package.

[0050] Referencing FIG. 3A, globbed chip-scale-packaged microelectronicdevice 38 comprises a semiconductor die 12 disposed over insulatingsupport 32. Walls 31 of support 32 define an opening through which bondwires 30 bond-out contacts 29 of die 12 to pads 34 of support 32.Outwardly projecting contacts or solder balls 14 of support 32 aredisposed across its outwardly facing surface 18, and arranged in anarray or grid in compliance with BGA industry standards. Encapsulationmaterial 36, such as epoxy, seals opening 31 for protecting bond wires30 and die 12. Hereinafter, encapsulation material 36 is referred to asan “encapsulant projection”. Although shown having a rounded uppersurface, encapsulant projection 36 may comprise alternative shapes, suchas, for example, a squared profile as might be provided by a mold.

[0051] In FIG. 3A, contacts 29 of semiconductor die 12 are located neara center region of the die. Alternatively, with reference to FIG. 3B,the contacts of die 12 might be located near a peripheral edge of thedie. To accommodate this alternative embodiment, an alternative support32 comprises a recess 13 that seats die 12 therein. Bond wires 30electrically interface the peripheral pads of the die to pads 34 of theinterposer 32 proximate recess 13. Conductive traces 35 of the supportcouple and re-route the central pads 34 to alternatively positionedoutwardly projecting-contacts 14. With reference to FIG. 3C, theoutwardly projecting contacts 14 of the chip-scale-package 38 have aheight h₁ greater than the height h₂ of encapsulant projection 36 In anexemplary embodiment, outwardly projecting contacts 14 have a height h₁of about 0.35 millimeters (about 0.8 times its width or “diameter”), andencapsulant projection 36 a height h₂ of about 0.1 to 0.3 millimeters.

[0052] Continuing with reference to FIGS. 3A-3C, when trying to seatsuch globbed chip-scale-packaged microelectronic device 38 over priorart BGA test inserts—i.e., an insert similar to that of FIG. 1—theencapsulant projection 36 of the package may confront a region of theupper surface of the insert to as to interfere with and prevent theoutwardly projecting contacts 14 of the device from engaging respectivepockets 16 of the prior art insert.

[0053] Recognizing this potential difficulty, the present inventionproposes a new test insert having a recess configured to receive withclearance a protrusion of such chip-scale-package. In an exemplaryembodiment of the present invention, with reference to FIG. 4, insert 10comprises recess 17 having a peripheral outline and depth capable ofreceiving with clearance an encapsulant projection of a globbedchip-scale-packaged microelectronic device while the outwardlyprojecting contacts of the device are seated in pockets 16 of theinsert. In a further exemplary embodiment, insert 10 forms part of atest jig for testing such globbed chip-scale-packaged devices. Wirebonds or flex-tab-tape electrically couple insert 10 to supportsubstrate 26 which, in turn, is in electrical communication with anexternal test system (not shown in FIG. 4). A method of forming suchinsert, in accordance with another exemplary embodiment of the presentinvention, is now described below with reference to FIGS. 5-13.

[0054] Referencing FIG. 5, substrate 40 comprises a semiconductorsubstrate, a dielectric substrate, or a layered combination thereof.Suitable exemplary substrates include silicon-on-glass,silicon-on-sapphire, germanium, gallium arsenide, or ceramic. In thecurrent application, the term “substrate” will be understood to mean anysupporting structure including, but not limited to, semiconductorsubstrates. Further, the term “substrate” or “semiconductor substrate”may also refer to any construction comprising semiconductor material,including but not limited to bulk semiconductive materials such as asemiconductor wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials).

[0055] In a preferred exemplary embodiment, further referencing FIG. 5,substrate 40 comprises mono-crystalline silicon having a <100>crystalline lattice-plane at surface 19 and a thickness of at least 500μm, and more preferably a thickness between 650 to 750 μm. Etchresistant material 42 such as silicon nitride is formed over surface 19of substrate 40. Etch resistant material 42 is provided a thicknessgreater than 100 angstroms, and more preferably between 500 to 3000angstroms, and is formed using known means such as chemical vapordeposition (CVD) or physical vapor deposition (PVD).

[0056] Moving on to FIG. 6, photoresist 44 is patterned over etchresistant material 42 using known photolithographic procedures toprovide openings that expose corresponding regions of etch resistantmaterial 42. Through these openings of the patterned photoresist 44, theexposed regions of the etch resistant material 42 are removed andopenings 46 formed in the layer of etch resistant material (hereinaftermask 42) as shown in FIGS. 7-8.

[0057] Referencing FIG. 9, exposed regions of substrate 40 are thenetched through the mask openings 46 to form pockets 16 and recess 17within the substrate. In a preferred exemplary embodiment, wheresubstrate 40 comprises mono-crystalline silicon having a <100>lattice-plane of orientation at surface 19, a potassium hydroxide (KOH)etch solution is used to anisotropically etch the substrate. Using suchanisotropic etchant, pockets 16 and recess 17 are formed with sidewallshaving a slope of between 40° to 70°, and typically 54° relative a planedefined by the substrate's surface 19.

[0058] Continuing with reference to FIGS. 9 and 10, recess 17 andpockets 16 are preferably etched simultaneously with a depth of at least10 μm, and more preferably between 15 to 150 μm. Additionally, thesidewalls that define recess 17 meet surface 19 of the substrate todefine a peripheral outline 15 encompassing an area greater that that ofany individual pocket 16, and more preferrably, greater that that of aplurality of the pockets. For example, pockets 16 are formed with awidth between 100 to 400 μm, and more preferably between 200 to 350 μm,while recess 17 provided a width of at least 500 μm and more preferablybetween 2,000 to 3,000 μm, and a length preferably between 4,000 to15,000 μm. In a preferred exemplary embodiment, pockets 16 have widthsslightly less than the diameter of the outwardly projecting contacts ofthe microelectronic to be seated therein.

[0059] After the etching the pockets 16 and recess 17, mask 42 isremoved and a dielectric 22 for example, an oxide, nitride, carbide orthe like—formed conformably over substrate 40, see FIG. 11. Dielectric22 is formed by a known deposition process such as, for example,chemical vapor deposition (CVD).

[0060] Preferably, dielectric 22 comprises silicon dioxide formed bythermal oxidation of underlying a silicon substrate 40. In such anexemplary embodiment, substrate 40 comprises silicon and is exposed toan oxidizing atmosphere comprising steam and oxygen at an elevatedtemperature (e.g. 950°). The oxidizing atmosphere oxidizes exposedportions of substrate 40 and forms an oxide layer conformally over thesubstrate's exposed surfaces. In an alternative embodiment, dielectric22 is formed by thermal decomposition of tetraethylortho-silicate(TEOS). Preferably, the dielectric (hereinafter, insulating layer 22) isformed with a thickness of between 0.5 to 5 μm.

[0061] Conductive layer 20 is formed over the insulating layer 22 and ineach of pockets 16. The conductive layer is patterned to provideconductive liners in pockets 16. The pockets (with conductive liners)are configured to engage the outwardly projecting contacts of achip-scale-packaged microelectronic device for enabling electricalcommunication with the microelectronic device when seated thereon. In apreferred exemplary embodiment, regions of the originally depositedconductive layer 20 associated with recess 17 are removed.Alternatively, regions of the conductive material within recess 17 canbe patterned to provide conductive traces within the recess.

[0062] Conductive layer 20 may comprise material of group IIIB throughVIIIB metals, such as (but not limited to) the refractory metals, e.g.,aluminum, iridium, copper, titanium, tungsten, tantalum, molybdenum, oralloys thereof. Conductive layer 20 might alternatively comprise otherelectrically conductive material such as, for example, metal-nitride oftitanium-nitride or a silicide such as titanium-silicide. In a preferredexemplary embodiment, conductive layer 20, at regions associated withpockets 16, comprises an upper layer of titanium over a lower layer ofaluminum. The upper layer selected to prevent permanent or chemicalbonding of the pocket liners to the conductive material of the outwardlyprojecting contacts to be seated thererin. These conductive materialsmay be formed using known metal deposition processes, e.g., sputter,CVD, or PVD deposition. Additionally, the conductive materials can bepatterned using known photolithographic, masking and etch procedures.

[0063] In another exemplary embodiment, conductive layer 20, at regionsassociated with bond pads 21, comprises a stack of two different layers,e.g., a lower barrier layer and an upper bonding layer to which wirebonds may be attached, as set forth in U.S. Pat. No. 5,592,736, issuedJan. 14, 1997, entitled “Fabricating An Interconnect For TestingUnpackaged Semiconductor Dice Having Raised Bond Pads”, which is herebyincorporated by reference. See also U.S. patent application Ser. No.09/110,554 filed Jul. 6, 1998, entitled “Metalized Recess In A SubstrateAnd Method Of Making The Same”, which is also incorporated herein byreference. In particular, the barrier and bonding layers are formulatedto prevent oxidation of conductive materials associated with theinterconnects, which oxidation might otherwise change the resistance ofits contacts. The bonding layer is selected to facilitate wire bondingthereto. In a preferred exemplary embodiment, the barrier layercomprises a metal such as platinum, titanium, tungsten, or alloysthereof. As patterned, certain portions of conductive layer 20 definetraces 23 while other portions define bond pad 21 in electricalcommunication with the conductive liners of pockets 16. Methods offorming the conductive material, traces and liners can be found in U.S.patent application Ser. No. 09/110,554, filed Jul. 6, 1998, entitled“Metalized Recess In A Substrate And Method Of Making The Same”, againincorporated herein by reference. In other more specific exemplaryembodiments, regions of the conductive layer 20 associated with the bondpads may comprise multiple layers of conductive material such as, forexample, a four layer stack (not shown) comprising titanium, tungsten,titanium and aluminum respectively.

[0064] In an exemplary embodiment, further referencing FIG. 11, bondpads 21 of insert 10 comprise a metal, such as aluminum or analuminum-titanium stack, deposited over select regions of conductivelayer 20. In an alternative embodiment, the bonding pads are patternedfrom a portion of conductive layer 20. These bond pads 21 serve aselectrical interface terminals for insert 10. Wire bonds, tab tape, orother suitable connection means are coupled to the bond pads of theinsert and provide electrical communication to external circuitry.

[0065] In a preferred exemplary embodiment, with reference to FIGS.12-13, pockets 16 of the insert include known blade structures 48. Bladestructures 48 allow pockets 16 to engage both small solder balls 14′ orlarge solder balls 14 (shown in phantom lines). Accommodating a varietyof solder ball dimensions, these pockets with blade structuresfacilitate reliable engagement and electrical coupling to BGA packagedmicroelectronic devices. U.S. Pat. No. 5,592,736, again incorporatedherein by reference, provides additional information regarding suchblades 48, and, in particular, teaches blade configurations thatpenetrate the outwardly-projecting contacts of a microelectronic deviceto a predetermine depth less than the height of the outwardly projectingcontacts, while, at the same time, minimizing surface damage andspreading of the outwardly projecting contacts.

[0066] Returning to FIG. 4, a globbed chip-scale-packagedmicroelectronic device 38 is seated upon insert 10. Recess 17 of theinsert comprises a peripheral outline greater than that of theencapsulant projection, and a depth preferably equal to that of pockets16. Accordingly, during test of the globbed chip-scale-packagedmicroelectronic device, recess 17 is able to receive the encapsulantprojection of the microelectronic device without contact, so as not tointerfere with the mechanical coupling and electrical connection ofpockets 16 with the outwardly projecting contacts 14 of themicroelectronic device.

[0067] In accordance with another exemplary embodiment of the presentinvention, with reference to FIG. 14, a test jig 59 comprises an insert10 within an assembly for testing a globbed chip-scale-packagedmicroelectronic device 38. Insert 10 is fixed to support substrate 26,which in-turn is fixed to a test head or base 48. Globbedchip-scale-packaged microelectronic device 38 is positioned over insert10, with outwardly projecting contacts 14 seated and engaged with theirrespective pockets 16 of the insert. Encapsulant projection 36 of themicroelectronic device extends into recess 17 of the insert withoutcontacting walls that define the recess. Wire bonds 28 couple conductivepads of insert 10 to conductive pads of support substrate 26. Socketcontacts 46 of the test jig electrically couple the circuit traces ofthe support substrate to terminal leads 47, which terminal leads are inelectrical communication with test circuitry 58 by way of bus 60.

[0068] In the illustrated exemplary embodiment, cover 54 acts togetherwith biasing member 52 and force plate 50 to apply a biasing forceagainst the globbed chip-scale-packaged microelectronic device 38,thereby forcibly engaging its outwardly projecting contacts 14 againstpockets 16 of insert 10. Cover 54 includes clips 53 and tabs 57. Tabs57, at the ends of clips 53, are received and captured by clamp ring 56for securing the cover 54 to base 48. Cover 54 preferably comprisesresilient metal, such as steel. Force plate preferably comprises a solidmaterial such as metal, plastic or ceramic. The force plate is shaped toengage and apply a force across various surfaces of the globbedchip-scale-packaged microelectronic device 38. Biasing member 52 isdisposed between the inside surface of cover 54 and force plate 50 toapply a force against force plate 50 when cover 54 is secured to base48. Biasing member 52 preferably comprises a resilient elastomericmaterial—e.g., silicone, butyl rubber, flourosilicone, andpolyimide—capable of exerting a biasing force over a continuedlife-span. Additional aspects concerning elements of test jig 59 and itsassembly are provided by U.S. patent application No. 09/______, filed______, entitled “Test Carrier With Variable Force Applying MechanismFor Testing Semiconductor Components” (98-0333), and U.S. Pat. No.5,796,264 entitled “Apparatus For Manufacturing Known Good SemiconductorDie”, which application and patent are incorporated herein by reference.

[0069] In accordance with another exemplary embodiment of the presentinvention, with reference to FIG. 15, a silicon insert 10 comprises avia filled with conductive material 62 connected to an underlying solderbump 66. Solder bump 66 is coupled to a surface 75 of the conductivematerial 62 within the via opening where walls 63 of the via meetsurface 41 of substrate 40. The filled via provides electricalcommunication between pocket 16 and solder bump 66. Solder bump 66 ofthe insert is disposed over conductive pad 68 of support substrate 26.Conductive material 62 comprises metal wetable by molten solder ofsolder bump 66. Likewise, conductive pad 68 of support substrate 26 alsocomprises metal wetable by the reflow of such solder. Accordingly, astep of heating solder bump 66 will re-flow the solder of the solderbump and wet pad 68 for joining the insert to the supporting substrate.During such reflow, the surface tension and cohesive forces of themolten solder reshape the solder, e.g., as illustrated by phantom lines70. This insert of FIG. 15 is capable of efficient manufacture by way ofanother exemplary embodiment of the present invention described belowwith reference to FIGS. 16-18.

[0070] Referencing FIGS. 16-18, mask 42 is formed over substrate 40using a known method of mask formation. Substrate 40 preferablycomprises monocrystalline silicon having a <100> lattice-plane oforientation at surface 19. Exposed portions of substrate 40 (i.e.,exposed per openings 46 of mask 42) are etched to form pockets 16 in thesubstrate. In an exemplary embodiment, the substrate is etched using ananisotropic etchant—e.g., a mixture of potassium hydroxide (KOH) andwater. With such anisotropic etchant, the <100> silicon lattice-surfaceof the substrate etches more rapidly than the other orientations so asto form sidewalls for the pockets having a slope of between 40 to 70degrees, and typically 54 degrees, relative a plane defined by surface19 of substrate 40.

[0071] As described before relative FIGS. 4-11, preferably, a recess(not shown in FIGS. 16-28) is formed in substrate 40 simultaneously withpockets 16. In such aspect, the pockets are configured to seat theoutwardly projecting contacts of a BGA component, and the recessconfigured to receive with clearance a protrusion of a BGA component.

[0072] Continuing with the present embodiment with reference to FIG. 19,the substrate is further processed to form via 61 between a floor ofpocket 16 and lower surface 41 of substrate 40. Via 61 comprisessidewalls 63 preferrably centered about a center axis (not shown) ofpocket 16. However, in alternative embodiments (not shown), via 61 ispositioned away from the center-axis of pocket 16. In a preferredexemplary embodiment, via 61 is formed with sidewalls 63 substantiallyperpendicular (90°) to lower surface 41 of substrate 40, and with adiameter of about 30-150 μm.

[0073] In the exemplary embodiment, via 61 is formed using a lasermachine. A suitable laser machine to form via 61 is a laser machinemanufactured by General Scanning of Summerville, Mass., designated byModel No 670-W. In an exemplary embodiment, the laser power to form via61 through a substrate of silicon (e.g., of 28 mil thickness) is a powerof about 2-10 watts per opening, at a pulse duration of about 20-25 ns,and repetition rate of up to several thousand pulses per second. Thespectrum for the laser beam can be standard infrared or green (e.g.,10.6 μm to 532 nm wavelength). Preferably, the laser beam is generatedby a NdYag or CO₂ laser of about 10.6 μm wavelength.

[0074] After forming via 61 in communication with pocket 16, referencingFIG. 20, a dielectric 22 is layered conformably over substrate 40. In aparticular embodiment, substrate 40 is exposed to an oxidizingenvironment to form an oxide dielectric 22 conformably over substrate40, including the walls defining pocket 16 and via 61. The oxidizingatmosphere, in an exemplary embodiment, comprises steam and oxygen (O₂)at an elevated temperature of, for example, 950° C. Preferably,dielectric 22 is formed with a thickness in a range of 0.5 to 5 μm. Inalternative embodiments, where substrate 40 comprises an electricallyinsulating material, such as ceramic or a glass filled resin, theformation of the dielectric insulating layer 22 may be eliminated.

[0075] Referring now to FIG. 21, a first conductive material 62 isformed conformably over substrate 40, including via 61 and the walls ofpockets 16. In an exemplary embodiment, conductive material 62 fills via61 and comprises metal wetable by solder. Preferably, conductive layer62 comprises copper of at least 5 μm thickness, and more preferably, athickness between 15-75 μm. Alternative metals for conductive material62 include gold, palladium, nickel, chromium, or alloys thereof.

[0076] After forming conductive material 62, second conductive material64 is formed over first conductive material 62, with a thickness greaterthan 500 angstroms and, more preferably, 600 to 20,000 angstroms. Thesecond conductive material comprises material different from the firstconductive material 62 and is selected to resist bonding to solder. Incertain exemplary embodiments, second conductive material 64 comprises ametal such as tungsten, titanium, platinum, titanium nitride ortitanium-tungsten. Conductive layers 62,64 are formed using knowndeposition processes, such as, for example, CVD, PVD, electrolytic orelectrolysis deposition.

[0077] Continuing with reference to FIGS. 22-24, mask 72 is formed overthe conductive layers and patterned appropriately to cover regions ofthe conductive materials associated with pockets 16. Mask 72 comprisesknown masking material, e.g., photoresist, nitride or other suitablemask material. With mask 72 over pockets 16, exposed regions of theconductive material are etched using known wet or dry etchants untilexposing insulating layer 22 (or alternatively substrate 40). Next, mask72 is removed, leaving pockets 16 lined with conductive material 62 and64 as shown by FIG. 24.

[0078] Moving on to FIGS. 25-28, a micro-bump 66 (referred toalternatively before relative to FIG. 15 as a solder bump) is formedover surface 41 of substrate 40 and in contact with exposed surface 75of conductive material 62 in via 61. In a preferred exemplaryembodiment, via 61 has a diameter of 30-150 μm. Additionally, micro-bump66 comprises a metal alloy—e.g., a lead/tin (PbSn) solder or alloy ofindiun/tin (InSn) or antimony/tin (SbSn)—that is formed on the outwardlyfacing surface 75 of the conductive material 62 at the via's opening.

[0079] In alternative exemplary embodiments, micro-bump 66 comprisesmetal of the group consisting of copper, nickel, gold and platinum, andis formed using known equipment and methods of the art, including forexample selective deposition, electroplating, electroless-plating,screen-printing or evaporation. U.S. Pat. No. 5,808,360, entitled “MicroBump Interconnect For Bare Semiconductor Dice”, issued Sep. 15, 1998,incorporated herein by reference, provides description of such exemplarymicro-bump structures and formation. One such method of formingmicro-bumps is now described below with reference to FIGS. 25-28.

[0080] Referencing FIGS. 25-26, stencil 78 is positioned over surface 41of substrate 40 and comprises opening 77 that is positioned over viacontact 75. Via contact 75 is understood to mean, and was referred tobefore as, the outwardly facing surface 75 of the conductive material 62within the via opening where walls 63 of via 61 meet surface 41 ofsubstrate 40. Continuing with the present embodiment, a solder drop 72is dispensed from a nozzle 74 over stencil 78 proximate the stencil'sopening 77. Squeegee-blade 80 (FIG. 26) squeegees drop 72 across andinto opening 77 of stencil 78. The height and width of opening 77 areselected in accordance with a desired solder volume for micro-bump 66.In an exemplary embodiment, opening 77 provides a pocket volume of about0.032 mm³.

[0081] Continuing with FIGS. 27-28, the stencil is removed, leavingstenciled solder 76 over and in contact with via contact 75, theoutwardly facing surface of the conductive material 62 at the via'sopening. Thereafter, heat is applied to the stenciled solder 76 so as toreflow the solder and form a rounded shape for micro-bump 66. In anexemplary embodiment, the solder comprises a lead/tin eutectic and isheated to a reflow temperature of about 183° C. In an alternativeembodiment, the solder comprises a 95:5 lead/tin mixture and is heatedto a reflow temperature of about 320° C. During the re-flow, it istheorized that the surface tension and cohesive forces of the moltensolder provide the forces operative to reshape the solder into ahemispherical or generally convex shape.

[0082] In a test jig, referencing FIGS. 15 and 29, silicon insert 10 ispositioned over support substrate 26 with the micro-bumps 66 over theirpads 68 of the support substrate 26. Thereafter, heat is applied tore-flow the solder microbumps 66 for wetting pads 68 of the supportsubstrate and securing silicon insert 10 to support substrate 26.Support substrate 26 and silicon insert 10 can then be employed in atest system, such as that portrayed by FIG. 29, for testing amicroelectronic device 38 having an array of outwardly projectingcontacts 14.

[0083] For the exemplary test system illustrated by FIG. 29, testcircuitry 58 sends electrical signals to the device under test by way ofbus 60, terminal leads 47, conductive traces 24 of support substrate 26,micro-bumps 66, via 61 and lined pockets 16 of insert 10. As describedbefore relative FIG. 14, cover 54 clips into clamp ring 56 by way oftabs 57 for compressing biasing member 52 to provide a force againstforce plate 50 which presses outwardly projecting contacts 14 ofmicroelectronic device 38 into pockets 16 of the silicon insert 10.

[0084] Thus, the present invention provides a new insert, method forforming an insert and method of testing a globbed chip-scale-packagedmicroelectronic device. Although the foregoing invention has beendescribed with respect to certain exemplary embodiments, otherembodiments will become apparent in view of the disclosure herein.Accordingly, the described embodiments are to be considered only asillustrative and not restrictive. The scope of the invention, therefore,is indicated by the appended claims and there combination in whole or inpart rather than by the foregoing description. All changes thereto whichcome within the meaning and range of the equivalent of the claims are tobe embraced within the scope of the claims.

What is claimed is:
 1. An insert for seating an electronic devicecomprising a chip-scale package having electrical-contact bumps and aprotrusion prjecting from a common side thereof, said insert comprising:a substrate having walls defining a plurality of pockets configured toreceive at least a portion of the electrical-contact bumps of saidchip-scale-package, other walls of said substrate defining a clearancerecess configured to receive with clearance the protrusion of saidchip-scale-package when the electrical contact bumps are at leastpartially received in said plurality of pockets; and conductive materialwithin at least a portion of at least some of said plurality of pockets.2. An insert according to claim 1, wherein said recess has a perimeterencompassing an area greater than any of said pockets.
 3. An insertaccording to claim 2, wherein said pockets each have a width less than400 μm and said recess has a width greater than 500 μm.
 4. An insertaccording to claim 3, wherein said pockets each have a width between100-400 μm, and said recess a width between 2,000-3,000 μm and lengthbetween 4,000 to 15,000 μm.
 5. An insert according to claim 3, whereinsaid pockets and said recess have substantially the same depth.
 6. Aninsert according to claim 5, wherein said depth is at least 10 μm.
 7. Aninsert according to claim 3, wherein said pockets and said recess have adepth between 15-150 μm.
 8. An insert according to claim 2, wherein saidrecess is disposed between at least two pockets of said plurality ofpockets.
 9. An insert according to claim 1, wherein said substratecomprises monocrystaline silicon.
 10. An insert according to claim 9,further comprising a layer of dielectric material disposed conformablyagainst said silicon of said substrate and beneath said conductivematerial.
 11. An insert according to claim 10, wherein said dielectricmaterial comprises an oxide.
 12. An insert according to claim 10,wherein said conductive material comprises at least one of the groupconsisting of refractory metal, refractory metal nitride, and refractorymetal salicide.
 13. An insert according to claim 1, wherein saidconductive material comprises at least one of the group consisting ofgroup IIIB through VIIIB metals.
 14. An insert according to claim 13,wherein said conductive material that lines said pockets is selected toresist bonding to the outwardly-projecting electrical-contact bumps ofsaid chip-scale-package.
 15. An insert according to claim 1, whereinsaid conductive material that lines said pockets is selected to resistbonding to solder.
 16. A ball-grid-array socket for seating amicroelectronic device having an array of contact-bumps and a protrusionprojecting from a common side thereof, said ball-grid-array socketcomprising: a substrate with a primary surface having a plurality ofpockets disposed in a pattern thereacross corresponding to said array ofcontact-bumps of the microelectronic device, said pockets configured toat least partially receive said contact-bumps of the microelectronicdevice, said primary surface of said substrate further defining a recessconfigured to receive and clear the protrusion of the microelectronicdevice when the contact bumps are at least partially received inrespective said pockets of said substrate, said recess disposed amongstsaid plurality of pockets; and electrically conductive material layeredconformably over at least a portion of said substrate including at leastsome of said plurality of pockets.
 17. A ball-grid-array socketaccording to claim 16, wherein said substrate comprises monocrystalinesilicon.
 18. A ball-grid-array socket according to claim 17, furthercomprising a layer of dielectric disposed conformably against saidsilicon substrate and beneath said electrically conductive material. 19.A ball-grid-array socket according to claim 18, wherein said dielectriccomprises an oxide.
 20. A ball-grid-array socket according to claim 17,wherein said silicon has a <100> lattice-plane of orientation at saidprimary surface.
 21. A ball-grid-array socket according to claim 16,wherein said walls defining said pockets are sloped with an angle ofabout 40-70 degrees relative a plane defined by said primary surface.22. An interconnect for electrically interfacing an electroniccomponent, said electronic component having a protrusion and a pluralityof outwardly-projecting contact-bumps extending outwardly from a frontsurface thereof, said interconnect comprising: a substrate having aprimary surface with a plurality of pockets configured to at leastpartially contact respective said outwardly-projecting contact-bumps ofsaid electronic component, said primary surface further having aclearance recess configured to receive with clearance the protrusion ofthe electronic component when said contact-bumps are at least partiallycontacting associated said plurality of pockets; and conductive materialpatterned over at least a portion of the primary surface of saidsubstrate and extending into at least one of said plurality of pockets.23. An interconnect according to claim 22, wherein said pocketsassociated with respective said outwardly-projecting contact-bumps eachhave a first width, said protrusion has a second width greater than saidfirst width, and said clearance recess has a width greater than saidsecond width for enabling clearance of said protrusion.
 24. Aninterconnect according to claim 23, wherein said clearance recess has adepth of at least 10 μm.
 25. An interconnect according to claim 24,wherein said substrate comprises silicon.
 26. An interconnect accordingto claim 25, wherein said silicon has a <100> plane of orientation atsaid primary surface.
 27. An interconnect according to claim 25, whereinsaid substrate has a thickness of at least 500 μm.
 28. An interposer forinterfacing an electronic component having a protrusion and a pluralityof contact-bumps that extend outwardly from a front face thereof, saidinterposer comprising: a substrate having a primary surface with aplurality of pockets disposed thereacross, said plurality of pocketsconfigured to at least partially receive respective said plurality ofcontact-bumps of said electronic component, said primary surface furthercomprising a recess configured to receive with clearance the protrusionof the electronic component when said contact-bumps are at leastpartially received within associated said plurality of pockets;conductive material patterned over the primary surface of said substrateincluding at least one of said plurality of pockets; and an electricalterminal disposed on said substrate and electrically coupled to said atleast one pocket by a portion of said patterned conductive material. 29.An interposer according to claim 28, wherein said substrate comprisessilicon.
 30. An interposer according to claim 29, wherein said siliconhas a <100> lattice plane of orientation at said primary surface.
 31. Aninterposer according to claim 30, wherein said walls that define saidpockets have a slope of about 40-70° relative said primary surface. 32.An interposer according to claim 31, wherein said one pocket thatreceives said protrusion has a depth of at least 10 μm.
 33. Aninterposer according to claim 32, further comprising a dielectric layerconformably layered over said substrate and beneath said patternedconductive material.
 34. An interposer according to claim 33, whereinsaid dielectric comprises oxide.
 35. An interposer according to claim33, wherein said substrate has an outer peripheral edge and saidelectrical terminal is disposed proximate said outer peripheral edge.36. A method of interfacing an electronic device comprising the stepsof: providing an electronic device having a plurality of contact-bumpsof a ball-grid-array and an encapsulant projection that extend outwardlyfrom a face thereof; providing a substrate having a primary surface witha plurality of pockets disposed thereacross corresponding to saidplurality of contact-bumps of the ball-grid-array of said electronicdevice, said primary surface further comrising a recess; disposing saidelectronic device over said substrate; contacting at least part of eachof said contact-bumps of said electronic device with respective saidplurality of pockets of said substrate; and receiving and clearing saidencapsulant projection of said electronic device within said recess ofsaid substrate.
 37. A method according to claim 36, further comprising astep of propagating an electrical signal between said substrate and saidelectronic device.
 38. A method according to claim 37, wherein said stepof propogating includes transferring said electrical signal between acontact-bump of the electronic device and the respective pocket of saidplurality engaged therewith.
 39. A method of testing an electronicdevice comprising steps of: providing a chip-scale-packaged electronicdevice, said chip-scale-package having a protrusion and a plurality ofoutwardly-projecting contact-bumps that extend outwardly from a facethereof; providing a substrate having walls that define a plurality ofpockets across a surface thereof, at least one of said plurality ofpockets configured to at least partially receive respective one of saidplurality of contact-bumps of the chip-scale-package, other walls ofsaid substrate defining a recess configured to receive the protrusion ofthe electronic device; coupling said electronic device to said substratewith said at least one contact bumps at least partially contactingassociated said plurality of pockets and said protrusion positionedwithin said recess without contacting the walls defining said recess;and propagating at least one electrical signal between said substrateand said electronic device.
 40. A method according to claim 39, furthercomprising a step of removing said electronic device from said substrateafter propagating the electrical signal.
 41. A method according to claim39, wherein an electrical signal is propagated between a contact-bump ofthe electronic device and a pocket of said substrate.
 42. A method offabricating an insert for interfacing an electronic device having aplurality of contact-bumps and a protrusion that extend outwardly from aface thereof, said method comprising the steps of: providing asubstrate; forming a plurality of pockets in said substrate; forming arecess in said substrate having a width and length, the width and lengthof said recess being greater than the respective widths of any of saidpockets; forming a layer of insulating material conformably over saidsubstrate, including said plurality of pockets; and forming conductivematerial over said insulating material, including at least a portion ofsaid pockets.
 43. A method according to claim 42, wherein said pluralityof pockets and said recess are formed in a single step of etching.
 44. Amethod according to claim 43, wherein said step of etching comprises ananisotropic wet etch.
 45. A method according to claim 44, wherein saidsubstrate comprises monocrystalline silicon with a <100> surface plane.46. A method according to claim 43, wherein said pockets and said recessare formed with a depth of at least 10 μm.
 47. A method according toclaim 46, wherein said pockets and said recess are formed with a depthof about 15-150 μm.
 48. A method according to claim 42, wherein saidstep of forming the conductive material over said substrate comprisesthe steps of: layering metal conformably over said substrate; andclearing portions of said metal from regions of said substratecorresponding to said recess.
 49. A method of fabricating aball-grid-array socket for an electronic device comprising achip-scale-package having an array of outwardly-projecting contact-bumpsand an encapsulant-projection, said method comprising the steps of:providing a substrate; etching said substrate and forming a trench insaid substrate and an array of pits in said substrate disposed on atleast two opposite sides of said trench, said array of pits formed to atleast partially contact respective said outwardly-projecting contactbumps of said chip-scale-packaged electronic device and said trenchformed with a length and a width greater than that of any pit of saidplurality to enable receipt with clearance of the encapsulant-protrusionof said chip-scale-packaged electronic device; forming an insulatinglayer conformably over said substrate, incuding said pits; formingconductive material in at least some of said pits; and forming aconductive trace on the substrate in electrical communication with theconductive material of at least one of said pits.
 50. A method accordingto claim 49, wherein said step of etching comprises an anisotropic wetetch.
 51. A method according to claim 50, wherein said substratecomprises monocrystalline silicon having a <100> surface plane.
 52. Amethod according to claim 49, wherein said pit and trench are formedwith a depth of at least 10 μm.
 53. A method according to claim 52,wherein said pit and trench are formed with a depth in the range of15-150 μm.
 54. A method according to claim 49, further comprising a stepof forming a via in said substrate.
 55. A method according to claim 54,wherein said via is formed in communication with a pit of said array ofpits.
 56. A method according to claim 54, wherein said via is formedbetween a floor of a pit of said array of pits and a surface of saidsubstrate opposite said array of pits.
 57. A method according to claim54, wherein said step of forming the via employs a laser beam.
 58. Amethod according to claim 54, wherein said via is formed with wallssubstantially perpendicular to a surface of said substrate.
 59. A methodaccording to claim 58, wherein sidewalls of said array of pits areformed with a slope between 40-70° relative said surface of saidsubstrate.
 60. A method according to claim 54, wherein said step offorming the insulating layer includes coating sidewalls of said via withinsulating material.
 61. A method according to claim 60, wherein saidstep of forming the insulating layer comprises a step of exposing saidsubstrate to an oxidizing environment.
 62. A method according to claim54, further comprising a step of forming conductive material within saidvia.
 63. A method according to claim 62, wherein said step of formingconductive material within said via employs chemical-vapor-deposition.64. A method according to claim 62, wherein said step of liningelectrically couples a pit to conductive material in said via.
 65. Amethod according to claim 62, wherein said step of forming conductivematerial in at least some of said pits comprises a step of depositingconductive material different from that within said via.
 66. A methodaccording to claim 54, further comprising a step of fixing a contactbump to an exposed surface of the conductive material in the via on aside of said substrate opposite said pocket.
 67. A method according toclaim 66, wherein said contact bump comprises a solder bump.
 68. Amethod according to claim 67, wherein said contact bump comprises atin/lead eutectic.
 69. An insert for interfacing an electronic devicehaving a plurality of outwardly-projecting-contacts, said insertcomprising: a substrate, walls of said substrate defining at least onepocket configured to receive an outwardly-projecting contact of theelectronic device, other walls of said substrate defining a via throughsaid substrate; conductive material disposed in said via; and secondconductive material disposed in said at least one pocket, and over theconductive material in said via.
 70. An insert according to claim 69,wherein said substrate comprises monocrystaline silicon.
 71. An insertaccording to claim 69, wherein opposing walls that define said pocketare inclined with an angle of about 40-70 degrees relative a planedefined by a surface of said substrate.
 72. An insert according to claim69, wherein the walls defining said via adjoin a floor of said pocket.73. An insert according to claim 69, further comprising dielectricbetween said conductive materials and said substrate.
 74. An insertaccording to claim 69, further comprising an electrical-contact-bumpdisposed upon said substrate and over the region defined by where saidvia meets a surface of said substrate opposite said pocket.
 75. Aninsert according to claim 74, wherein said electrical-contact-bumpcomprises solder.
 76. A BGA test socket for temporarily engaging aplurality of outwardly-projecting contacts of a BGA of a microelectronicdevice, said test socket comprising: a substrate, first walls of saidsubstrate defining a pocket configured to seat an outwardly-projectingcontact of the microelectronic device, and second walls of saidsubstrate defining a passage through said substrate in communicationwith said pocket; first conductive material within at least a portion ofsaid passage; and second conductive material conformably layered in atleast a portion of said pocket and over said first conductive material.77. A BGA test socket according to claim 76, wherein said substratecomprises silicon having a <100> lattice-plane of orientation at anoutwardly facing surface thereof.
 78. A BGA test socket according toclaim 76, wherein sidewalls of said walls that define said pocket aresloped about 40-70 degrees relative a surface of said substrate.
 79. ABGA test socket according to claim 76, wherein the walls defining saidpassage meet a wall of said walls defining said pocket.
 80. A BGA testsocket according to claim 76, further comprising a layer of insulatingmaterial between said first and said second conductive materials andsaid substrate.
 81. A BGA test socket according to claim 76, wherein thewalls of said passage meet a lower surface of said substrate to definean aperature and said BGA test socket further comprises a contact-bumpfixed to said substrate over said aperature and electrically coupled tothe first conductive material within said passage.
 82. A BGA test socketaccording to claim 81, wherein said contact-bump comprises reflowableconductive material.
 83. A BGA test socket according to claim 82, wherinsaid contact-bump comprises a tin/lead alloy.
 84. A BGA test socketaccording to claim 82, further comprising a support substate having aconductive contact pad, said substrate fixed to said support substratewith said contact-bump joined to said conductive contact pad.
 85. A BGAtest socket according to claim 84, wherein said substrate comprisesmono-crystaline silicon and said support substrate comprises dielectricmaterial.
 86. A method of forming a BGA socket for testing amicroelectronic device comprisin a chip-scale-package having a pluralityof outwardly-projecting-contacts, said method comprising steps of:providing a substrate; forming a pocket in said substrate configured toat least partially receive an outwardly-projecting-contact of saidchip-scale- packaged microelectronic device; forming a via through saidsubstrate; forming first electrically conductive material in said via;and depositing second electrically conductive material in at least aportion of said pocket, including a portion over the first electricallyconductive material in said via.
 87. A method according to claim 86,wherein said step of forming said pocket comprises forming sidewalls forsaid pocket that are sloped about 40-70° relative a surface of saidsubstrate.
 88. A method according to claim 86, wherein said substratecomprises monocrystaline silicon having a <100> lattice-plane oforientation at a surface thereof.
 89. A method according to claim 86,further comprising a step of forming an insulating layer over saidsubstrate including said pocket and said via.
 90. A method according toclaim 89, wherein said step of forming an insulating layer comprises astep of exposing said substrate to an oxidizing atmosphere.
 91. A methodaccording to claim 86, wherein said step of forming first conductivematerial in said via comprises a step of chemical-vapor-deposition. 92.A method according to claim 86, wherein said second electricallyconductive material is different from said first electrically conductivematerial.
 93. A method according to claim 86, further comprising a stepof fixing said substrate to a support substrate with said pocket facingaway from said support substrate.
 94. A method according to claim 86,further comprising a step of forming a conductive-contact on a side ofsaid substrate opposite said pocket, said conductive-contact coupled toa portion of said first electrically conductive material in said via.95. A method according to claim 94, further comprising the steps of:providing a support substrate having a conductive-pad; and joining theconductive-contact of said substrate to the conductive-pad of saidsupport substrate.
 96. A method according to claim 95, wherein theconductive-contact of said substrate comprises a flowable metal alloyand the conductive-pad of said support substrate comprises conductivematerial wetable by said flowable metal alloy, and said step of fixingsaid substrate to the support substrate comprises the steps of:positioning the conductive-contact of said substrate in contact with theconductive-pad of said support substrate; heating and re-flowing theflowable metal alloy of the conductive-contact; and wetting theconductive-pad of said support substrate with the heated re-flow of saidflowable metal alloy.
 97. A method according to claim 96, wherein thefirst conductive material is selected to be wetable by reflow of theflowable metal alloy of said conductive-contact.
 98. A method accordingto claim 97, wherein the second conductive material is different fromsaid first electrically conductive material.
 99. A method according toclaim 98, wherein the second electrically conductive material isselected to resist bonding to the outwardly-projecting-contacts of achip-scale-packaged microelectronic device.
 100. A method according toclaim 98, wherein the second electrically conductive material isselected to resist bonding to solder.
 101. A method according to claim86, wherein walls defining said via are formed substantiallyperpendicular to an upper surface of said substrate and sidewalls ofsaid pocket are sloped with an angle between 40-70° relative to saidupper surface.
 102. A method according to claim 101, wherein the wallsdefining said via join a floor of said pocket.
 103. A method of testinga microelectronic device, said method comprising: providing amicroelectronic device having a plurality ofoutwardly-projecting-contacts of a BGA; providing a test insertcomprising a silicon substrate having walls that define a plurality ofpockets configured to at least partially receive respective saidplurality of outwardly-projecting-contacts, other walls of said siliconsubstrate defining a via extending through said silicon substrate, firstconductive material in said via and at least a portion of at least oneof said pockets, and a conductive-contact on a side of said siliconsubstrate opposite said pocket and electrically coupled to said pocketby way of said via; fixing said test insert to a support substrate withthe conductive-contact of said test insert coupled to a conductive-padof said support substrate; disposing said microelectronic device oversaid test insert with the plurality of pockets of said test insertremovably coupled to respective ones of said plurality ofoutwardly-projecting-contacts of the microelectronic device; andpropagating an electrical signal between said support substrate and saidmicroelectronic device by way of said test insert.
 104. A methodaccording to claim 103, wherein the conductive-contact of said testinsert comprises a flowable metal alloy and the conductive-pad of saidsupport substrate comprises conductive material wetable by said flowablemetal alloy, and said step of fixing said test insert to the supportsubstrate comprises the steps of: positioning the conductive-contact ofsaid test insert in contact with the conductive-pad of said supportsubstrate, heating and re-flowing the flowable metal alloy of saidconductive-contact, and wetting the conductive-pad of said supportsubstrate with the re-flow of said flowable metal alloy.
 105. A methodaccording to claim 104, wherein the conductive-contact of said testinsert comprises a solder bump.
 106. A method according to claim 103,further comprising a step of forceably biasing said microelectronicdevice against said test insert to facilitate electrical coupling of theplurality of pockets of said test insert with respective ones of saidplurality of outwardly-projecting-contacts of the microelectronicdevice.